Rumor 1: The A10 will be manufactured at TSMC in a 10 nm process

According to Apple, the iPhone 7 SoC will actually contain 3.3 billion transistors instead of 2 billion (Apple A9) . The A9 has a silicon area of 104 ^mm2 in TSMC's 16 nm FF+ process (only 96 ^mm2 in Samsung's 14 nm FF process), so that the area in identical production could even slightly exceed the previous record holder, the 45 nm Apple A5X from the 3rd generation iPad and its 165 ^mm2. Technically, this is not a problem at all; Intel's Xeon server processor of the Haswell generation, for example, accommodates its 5.69 billion transistors on 662 ^mm2 of silicon.

The fact is: TSMC is still as far away from 10 nm mass production as FC Bayern is from relegation to League 2.

Rumor 2: The A10 adapted ARM's Big.LITTLE architecture

It is true that, for the first time in an iPhone, there will be a quad-core CPU architecture with 2 "large" and 2 "small" energy-saving CPUs, to which the workloads are allocated depending on the CPU load. However, this is by no means ARM's Big.LITTLE implementation, as there are significant differences:

(a) ARM's original concept was based on operating system-controlled switching between the Big and LITTLE clusters with corresponding latency times. Apple has designed its own hardware block for switching, which makes the CPU clusters transparent for the application. In fact, an iOS app still only sees 2 CPUs without knowing which cluster it is currently running on.

b) New methods used in the Android environment have enhanced Big.LITTLE to such an extent that any CPU configurations can now be created, e.g. with 4 Big and 4 LITTLE CPUs, 1-4 Big and 1-4 LITTLE CPUs can be activated in parallel in almost any combination. The originator of this concept extension was Samsung. Here too, the operating system plays an important role in the activation/deactivation of CPU clusters or individual CPUs.

Rumor 3: The microarchitecture of the A9 CPUs has not been changed

Many colleagues are apparently of the opinion that the ARMv8-compatible microarchitecture of the Apple A9 called "Twister" has not been changed, but that the increase in computing power (40% according to Apple) would be achieved exclusively via a higher clock frequency. With 1.85 GHz in the A9, the A10 CPUs would therefore have to be clocked at almost 2.6 GHz.

Even if the new quad-core architecture can be imagined to reduce the thermal load on the SoC (the basic problem is by no means battery life as always claimed, but heat dissipation from the silicon plate at maximum clock frequency), an increase to a maximum of 2 GHz is realistic - the rest comes from a further improved microarchitecture called "Hurricane". We assume that the usual adjustments to the CPU architecture (the table shows the improvements of "Twister" compared to "Swift" (A6), "Cyclone" (A7) and "Typhoon" from the Apple A8) have been made and that the memory latencies have also been further reduced.