Figure 2: The measurement results of the system with TCC-capable Intel Core i5-1145GRE processor and extended DFVS functions.

© Intel

In such a system architecture, the GPOS is normally treated as Best Effort (BE) and aims for maximum peak performance, while the RTOS aims for the highest possible quality of service in terms of determinism. With the new hardware possibilities in the area of DVFS, such requirements can also be realized, as the following analysis shows by way of example.

Test setup and implementation

The test setup (Figure 1) simulates a typical use case in which a best-effort application and a real-time application are executed in parallel on one processor.

Figure 3: If the clock frequencies are changed using the pulsed BE application on a system with an older processor (Intel Core i5-8265U), this affects all cores.

© Intel

The two applications run on different computing cores. While the real-time application runs on cores with a fixed frequency, the computing cores for the BE application are configured in such a way that the clock frequencies can be changed dynamically, even into the turbo frequency range. A native, up-to-date Linux with preempt RT patch is used for this. The real-time cores are isolated from the BE cores by Linux directives. The well-known open source application Cyclictest is used as the real-time application. This application is well suited to describing important aspects of the real-time behavior of a system, such as that used by OSADL for 24×7 long-term studies. Cyclictest determines the jitter behavior of interrupts. This jitter can be influenced by hardware, firmware, the operating system, but also by BE applications.

In the test setup, the CPU load of a BE application is simulated on one of the BE cores using a stress-ng CPU stressor. A periodically repeated calling and stopping of stress-ng ensures that a P-state change, i.e. frequency changes, take place.

In an initial comparison, measurements were first carried out on a system with a current Intel TCC-capable processor and extended DVFS functions, in which DVFS functions such as Intel SpeedStep, Intel Speed-Shift and Intel Turbo Boost technology were deactivated in the BIOS. Measurements were then carried out in which these functions were reactivated. In addition, the processor clock frequencies were measured over time.
In a comparison, the measurements were carried out with the same test setup on an older processor that supports neither TCC nor one of the extended DVFS functions.

Figure 2 shows the measurement results of the system with a TCC-capable processor and extended DFVS functions. The processor has a base frequency of 2.6 GHz and a maximum turbo frequency of 4.1 GHz. As can be seen from the frequency diagrams, dynamic frequency changes into the turbo frequency range take place in the second scenario with activated BIOS functions. However, as can be seen in the histogram shown, the effects of this BIOS application with frequency changes are negligible. The maximum latencies differ by 1 µs and are less than 10 µs in both scenarios.
The graphs on the system with the older processor are completely different (Fig. 3). If the frequencies remain constant, the maximum latencies in the histogram correspond to those in Figure 2. However, if the clock frequencies are changed using the pulsed BE application, this has the expected effect on all computing cores. As the frequencies in the scenario with frequency changes are higher than in the scenario with constant frequency, no increase in maximum latencies would be expected from the resulting increases in clock frequency on the real-time cores. However, the histogram shows that the maximum latencies increase from 7 µs to 23 µs. The comparison of the histogram in Figure 2 with that in Figure 3 illustrates the improvement in the DVFS area with regard to the real-time capability of some current processor generations compared to older ones.

The tests carried out confirm that the DVFS hardware properties of some modern processors make it possible to configure consolidated applications flexibly on IPCs. Real-time requirements of the OT world, which require fixed processor frequencies, can be combined with requirements from the IT world, such as dynamically demand-oriented high computing performance at peak times. At the same time, computing cores can be downclocked with idle processes without significantly influencing the real-time behavior on the real-time-critical computing cores. This opens up interesting new possibilities for customer-specific configurations.