FPGA-in-the-loop
Acceleration of verification
MathWorks introduces new features in HDL Verifier to accelerate verification through FPGA-in-the-loop (FIL). Thanks to the new FIL functions, faster communication with the FPGA board and simulation at a higher clock frequency should be possible.
According to the manufacturer, system engineers and developers can now quickly and reliably verify and validate whether an FPGA design works exactly as expected in the system - and that saves development time.
The HDL Verifier for FIL verification automates the setup and connection of MATLAB and Simulink test environments with designs that are executed on FPGA development boards. This allows users to create high-fidelity cosimulations of the FPGA design running on the actual hardware, using the same test environment as for development.
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