Cooperation
Siemens and Nvidia are accelerating Chip Testing
Siemens and Nvidia have significantly accelerated the verification of AI chips. With the help of FPGA-based prototypes, tens of trillions of design cycles could be tested within a few days before production. This should improve the development and reliability of complex SoCs.
Siemens and Nvidia have presented a method that can be used to significantly expand the verification of complex AI and ML chips. It is based on the combination of the hardware-supported verification system Veloce proFPGA CS from Siemens with an optimized chip architecture from Nvidia.
According to the companies, several tens of trillions of design cycles could be recorded within a few days - even before a physical chip is manufactured. This order of magnitude is well beyond the capabilities of conventional verification processes: Simulation and emulation usually only achieve millions to a few billion cycles in a practicable time.
The technology is based on FPGA prototyping. Such systems make it possible to perform verification tasks significantly faster than purely software-based approaches. The requirements for modern AI and ML SoCs in particular are increasing considerably due to growing chip and software complexity.
As part of the existing partnership, the development aimed to increase the scalability of verification and test large workloads at an early stage. This allows developers to detect errors earlier and optimize designs even before the first silicon is produced.
"By integrating Nvidia's performance-optimized chip architectures with Siemens' Veloce proFPGA CS, developers can capture trillions of cycles in a matter of days, providing the scalability needed to ensure the reliability of next-generation AI."
Companies see the ability to process trillions of cycles in a short time as a key factor in meeting development times and quality requirements in the semiconductor industry.
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